The present invention relates to a data backup memory that temporarily stores input data synchronously with a lock signal like a flip flop that is implemented by means of a semiconductor integrated circuit.
In recent years, technologies for semiconductor integrated circuits such as LSIs have been significantly improved, with their operating frequencies remarkably increased. However, further improvement of the performance of semiconductor integrated circuits is continuously demanded; power consumption is required to be lower, and operations are required to be faster. That is, for design of semiconductor integrated circuits, both faster operations and lower power consumption are required.
One of the basic elements constituting such a semiconductor integrated circuit is a data backup memory operating synchronously with a clock signal; such a data backup memory is represented by a flip flop. That data backup memory is a very basic circuit for a semiconductor integrated circuit, so that various circuits have been proposed to increase the operation speed and reduce the power consumption. An example of known data backup memories is U.S. Pat. No. 5,917,355 entitled xe2x80x9cEdge-triggered staticized dynamic flip-flop with conditional shut-off mechanismxe2x80x9d.
The conventional data backup memory as described above will be described below with reference to drawings.
FIG. 7 is a circuit diagram showing the configuration of a conventional data backup memory. In this figure, reference numeral 1001 denotes a P channel transistor that remains on to precharge a first precharge node 1041 while a clock signal terminal (CK) 1031 is set to zero. Reference numerals 1021 and 1022 denote inverters that delay a signal from the clock signal terminal (CK) 1031 for a fixed period of time to generate a delayed clock signal (CKD) 1042. Reference numeral 1027 denotes a two-input logical-AND denying circuit using the first precharge node 1041 and the delayed clock signal (CKD) 1042 as an input and using a stop signal (S) 1043 as an output. The stop signal (S) 1043 from the circuit 1042 is set to zero only while both the first precharge node 1041 and the delayed clock signal (CKD) 1042 are set to one.
Reference numerals 1011 to 1013 denote N channel transistors connected together in series and which discharge the first precharge node 1041 when all of them are on. Specifically, if the first precharge node 1041 is set to zero or the delayed clock signal (CKD) 1042 is set to zero, and when the N channel transistor 101 is on and an input data terminal (D) 1033 is set to one, the N channel transistor 1012 is turned on. In this case, when the clock signal terminal (CK) 1031 is set to one, the N channel transistor 1013 is turned on.
Reference numerals 1023 and 1024 denote inverters that can retain the value for the first precharge node 1041 softly. When the P channel transistor 1001 is turned on, the first precharge node 1041 is precharged. When all the N channel transistors 1011 to 1013 are turned on, the first precharge node 1041 is discharged. The term xe2x80x9cretain softlyxe2x80x9d means that the value for the first precharge node 1041 is retained when the P channel transistor 1001 is off and when at least one of the N channel transistors 1011 to 1013 is off.
Reference numeral 1002 denotes a P channel transistor that remains on to precharge the second precharge node 1051 while the first precharge node 1041 is set to zero. Reference numerals 1014 and 1015 denote N channel transistors connected together in series and which discharge a second precharge node 1051 when both of them are on. Specifically, if the clock signal terminal (CK) 1031 is set to one, the N channel transistor 1015 is turned on. If the first precharge node 1041 is set to one, the N channel transistor 1014 is turned on.
Reference numerals 1025 and 1026 denote inverters that can retain the value for the second precharge node 1051 softly.
The conventional data backup memory configured as described above constitutes a flip flop that writes a value to the input data terminal (D) 1033 at a rising edge of the clock signal terminal (CK) 1031. Specific operations of the data backup memory will be described below.
First, the operation performed while the clock signal from the clock signal terminal (CK) 1031 is zero will be described.
At this time, the P channel transistor 1001 is on, the N channel transistor 1013 is off, and the first precharge node 1041 is set to one because a precharge path is open, while a discharge path is closed.
At this time, since the first precharge node 1041 is set to one, while the clock signal terminal (CK) 1031 is set to zero, both the precharge path and the discharge path are closed, so that the inverters 1023 and 1024 retain the previous value of the second precharge node 1051 softly.
Next, the operation performed after the clock signal has risen from zero to one and before the delayed clock (CKD) 1042 rises from zero to one will be described.
At this time, the P channel transistor 1001 is off, and the N channel transistor 1013 is on. In the first precharge node 1041, the precharge path is closed, and the discharge path is open when the input data terminal (D) 1033 is set to one, and is closed when the input data terminal (D) 1033 is set to zero.
That is, when the input data terminal (D) 1033 is set to one, the first precharge node 1041 is discharged. When the input data terminal (D) 1033 is set to zero, both the precharge path and the discharge path are closed, so that the inverters 1023 and 1024 retain value for the first precharge node 1041 softly.
In other words, if the input data is one, a value zero is written to the first precharge node 1041. If the input data is zero, a value one is written to the first precharge node 1041.
Further, when the value zero is written to the first precharge node 1041, the P channel transistor 1002 is turned on, while the N channel transistor 1014 is turned off, so that the value one is written to the second precharge node 1051. When the value one is written to the first precharge node 1041, the P channel transistor 1002 is turned off, while the N channel transistor 1015 is turned on. Since the N channel transistor 1014 is on, the value zero is written to the second precharge node 1051.
Finally, a description will be given of the operation performed when the clock signal is one and when the delayed clock signal (CKD) 1042 is one.
At this time, if the first precharge node 1041 is set to one, the stop signal (S) 1043 is zero. Accordingly, in the first precharge node 1041, since both the precharge path and the discharge path are closed, the inverters 1023 and 1024 retain the value one softly. If the first precharge node 1041 is set to zero, the precharge path is closed whether the discharge path is open or closed, so that the first precharge node 1041 is set to zero.
Further, when the first precharge node 1041 is set to, zero, the P channel transistor 1002 is turned on, while the N channel transistor 1014 is turned off, so that the second precharge node 1051 is set to one. When the first precharge node 1041 is set to one, the P channel transistor 1002 is turned off, the N channel transistor 1015 is turned on and the N channel transistor 1014 is turned on, so that the second precharge node 1051 is set to zero.
As described above, in the conventional data backup memory configured as described above, the value for the input data terminal (D) 1033 is written to the memory synchronously with the rising edge of the clock signal from the clock signal; terminal (CK) 1031, whereas the data retaining operation is performed during the other periods.
In this case, the value of the second precharge node 1051 is output from the output data terminal (Q) 1034 as an output data signal.
Due to the constitutional characteristic (the N channel transistor 1012 to which the input data terminal (D) 1033 is connected and the N channel transistor 1013 to which the clock signal terminal (CK) 1031 is connected are connected in series) of this conventional data backup memory, the setup time for this memory is ideally zero. Further, the worst value of the delay time required before the output signal from the input data terminal (D) 1033 is written to the second precharge node 1051 is the sum of the time required by the three N channel transistors 1011 to 1013 connected together in series to discharge the first precharge node 1041 and the delay time required by the P channel transistor 1002 to precharge the second precharge node 1051.
When, however, the conventional data backup memory as described above is used as a flip flop to design an LSI circuit, and when an attempt is made to increase the operating frequency of the circuit, a clock signal (timing control signal) having a frequency as high as the operating speed of the circuit must be supplied. Thus, problems of such a data backup memory are that a clock signal generating circuit provided must generate a high frequency and that a clock of a high frequency must be accurately distributed within the LSI.
Another problem is that the clock signal of a high frequency as described above may increase the power consumed by the clock generating circuit and a clock distributing circuit.
The present invention solves these conventional problems, and an object of the present invention is to provide a data backup memory that serves, if it is used to design an LSI, to reduce the frequency of a timing control signal supplied to the LSI to half of the conventional value and to substantially reduce the power consumption of the LSI associated with the timing control signal and the loads on a timing control circuit.
To attain this object, the present invention provides a data backup memory using as input a timing control signal having a period indicating a first phase and a period indicating a second phase as well as a data signal that can assume a first state and a second state, to process the data signal synchronously with the timing control signal and temporarily store the state of the data signal, the data backup memory characterized by comprising a first precharge node, second precharge node, a first precharge circuit, a second precharge circuit, a first discharge circuit, and a second discharge circuit, the first precharge circuit increasing a potential at the first precharge node up to and above a first boundary value during the first phase of the timing control signal, the first discharge circuit reducing the potential at the first precharge node below the first boundary value while the input data signal is in the second state during the second phase period of the timing control signal, the second precharge circuit increasing a potential at the second precharge node up to or above a second boundary value while the potential at the first precharge node is below the first boundary value, the second discharge circuit reducing the potential at the second precharge node below the second boundary value while the potential at the first precharge node is equal to or above the first boundary value during the second phase period of the timing control signal, the potential at the second precharge node being used as an output data signal.
Further, the present invention provides a data backup memory using as input a timing signal having a period indicating a first phase and a period indicating a second phase as well as a data signal that can assume a first state and a second state, to process the data signal synchronously with the timing control signal and temporarily store the state of the data signal, the data backup memory characterized by comprising a pulse signal generating circuit, a first precharge node, a second precharge node, a first precharge circuit, a second precharge circuit, a first discharge circuit, and a second discharge circuit, the pulse signal generating circuit outputting a pulse signal having a first pulse potential period corresponding to a fixed period from a point of time of a change in the timing control signal from a first phase period to a second phase period and from a point of time of a change therein from the second phase period to the first phase period as well as a second pulse potential period that is different from the first pulse potential period, the first precharge circuit increasing a potential at the first precharge node up to and above a first boundary value during the second pulse potential period of the pulse signal, the first discharge circuit reducing the potential at the first precharge node below the first boundary value while the input data signal is in the second state during the first pulse potential period of the pulse signal, the second precharge circuit increasing a potential at the second precharge node up to or above a second boundary value while the potential at the first precharge node is below the first boundary value, the second discharge circuit reducing the potential at the second precharge node below the second boundary value while the potential at the first precharge node is equal to or above the first boundary value during the first pulse potential period of the pulse signal, the potential at the second precharge node being used as an output data signal.
The above configuration ideally zeroes the setup time, and reduces the worst value of the delay time before the input data is written to the second precharge node as an output signal.
Thus, if the present data backup memory is used to design an LSI, the circuit can be designed while reducing the above delay time compared to the prior art, and the circuit configuration can be miniaturized compared to the prior art to reduce the scale of the LSI circuit.
Further, the input data can be written to the memory at the point of time of a change from the first phase period to the second phase period and at the point of time of a change from the second phase period to the first phase period. Accordingly, when this data backup memory is used in an LSI, operating timings based on a frequency double that of the timing control signal supplied to the LSI can be supplied to circuits in the LSI.
Thus, if the present data backup memory is used to design an LSI, the frequency of the timing control signal supplied to the LSI can be reduced to half of the conventional value, the power consumption of the LSI associated with the timing control signal can be substantially reduced, and the loads on a timing control signal generating circuit can be substantially reduced.